1. Technical Field
The present invention relates to a semiconductor device, a manufacturing method of the semiconductor device, and the like.
2. Related Art
A tub isolation method in which an N-type buried diffusion layer and a relatively high concentration N-type impurity diffusion region (N-plug) that extends from a semiconductor surface to the buried diffusion layer are formed in a P-type semiconductor and a well isolation method in which a relatively low concentration N-well is formed in a P-type semiconductor, for example, are known as a method of isolating a plurality of circuit elements in a semiconductor device.
The tub isolation method is appropriate for manufacturing a semiconductor device including a bipolar transistor or a zener diode, because the parasitic resistance from the semiconductor surface to the buried diffusion layer is reduced by the high concentration plug. On the other hand, the well isolation method is appropriate for manufacturing a semiconductor device mainly including a CMOS field effect transistor or an LD (Lateral Double-diffused) MOS field effect transistor, because an element arrangeable region is increased and a distance between elements can be reduced by not having the plug.
An LDMOS field effect transistor that is formed in a first impurity region 21n is illustrated in FIG. 1 in JP-A-2014-187275 (Paragraphs 0021-0022). The transistor includes a body region 26p located in the first impurity region 21n, a source region 27n and a body contact region 28p that are located in the body region 26p, a gate insulating film 33 located on an end portion of the body region 26p, a gate electrode 34 located on the gate insulating film 33, and a drain region 29n located in the first impurity region 21n.
The first impurity region 21n is isolated from a base layer 10p by a first buried diffusion layer 11n in a thickness direction of the semiconductor substrate 30. Also, the first impurity region 21n is isolated from other circuit elements located in an epitaxial layer 20p, in a direction along a first surface 31 of the semiconductor substrate 30, by a first conductivity type second impurity region (N-plug) 22n and a second conductivity type second buried diffusion layer 12p and fifth impurity region 25p.
However, because the N-plug is formed by thermally diffusing N-type impurities, when the N-plug that extends from the semiconductor surface to the buried diffusion layer in a vertical direction is formed, the N-plug extends in a horizontal direction as well. Accordingly, in a semiconductor device in which a plurality of different types of circuit elements are mounted together, when the N-plug is formed for each of the circuit elements, the element arrangeable region is reduced. Also, when an attempt is made to mount a plurality of different types of circuit elements together in the semiconductor device, processes for forming dedicated impurity diffusion regions for respective circuit elements increase, and the manufacturing cost of the semiconductor device increases due to the increased number of masks and processes.